1. Field of the Invention
The present invention generally relates to integrated circuits, and more particularly to reducing parasitic capacitance of a finFET semiconductor device.
2. Background of Invention
As integrated circuits continue to scale downward in size, a fin field effect transistor (finFET) is becoming more widely used. A typical finFET device may be fabricated with either a gate first process flow or a gate last, or replacement gate, process flow. Typically, a gate first process flow may include forming fins in a substrate, depositing a gate stack including a high-k dielectric and one or more gate metals, and finally etching the final gate structures. Alternatively, a replacement gate (RG) process flow may include the use of a dummy gate stack. In both cases, a gate electrode of the final finFET structure may occupy most of the space between adjacent fins in a gate region of the finFET. Furthermore, an epitaxially grown region (EPI region) may be formed above the ends of the fins not covered by the gate, for example source-drain regions. The EPI region may effectively merge the source-drain regions of adjacent devices, and in doing so, may occupy the space between adjacent fins. Therefore, the space between adjacent fins in the source-drain regions may be occupied with EPI region, and the space between adjacent fins in a gate region may be occupied by the gate electrode. In most cases, the source-drain regions may be coupled with two opposite sides of the gate region, with a spacer to electrically insulate the gate region from the source-drain regions.
The configuration of the EPI region and the gate electrode separated by the spacer may unintentionally form a capacitive structure in which two electrical conductors are separated by an insulator. This configuration may result in undesirable parasitic capacitance which may typically be referred to as gate-to-EPI capacitance. The gate-to-EPI capacitance may add to the total capacitance associated with the device and reduce the switching speed of the device.
Therefore, it may be desirable, among other things, to reduce the gate-to-EPI capacitance.